Design Engineer Five Steps to Realize FlexRay Robust Network Topology

FlexRay has begun to take advantage of single-channel high-speed powertrain, driver assistance and automotive electronics for increased comfort. In the new BMW X5, FlexRay is used in suspension control, allowing engineers and developers to use this fault-tolerant deterministic protocol in safe driving with dual communication channels and bus monitoring. There is a gradual adaptation process that reduces the associated risks.

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In the development of FlexRay applications, design engineers can build a robust network topology in five basic steps.

Step 1: First, you must define the number of nodes on the vehicle chassis and their assumed positions, and then determine the cable length required to implement a passive bus without stubs (a topology known as "daisy chain"). The terminal is the cable terminal, as shown in Figure 1. If the cable length is less than 10 meters, the topology is completed and it is considered to be usable for series production.

Step 2: Once the cable length is found to be greater than 10 meters, the “active star” topology should be considered (see Figure 2). If the cable length exceeds 20 meters, the active star must be introduced. The simplest active star type has only two branches, put the harness? ? For two electrical decoupling components. Because the active star is enhanced by NXP's TJA1080 transceiver (the first of its kind for the BMW X5), the total number of transceivers required has only increased by one.

Step 3: If the application can continue to work after a collision accident, the collision sensitive nodes of the system should be distributed on different branches (see Figure 3). In this way, once the cable is squeezed or clamped to a differential voltage, only the data transmission of the affected branch is interrupted, but the active star will ensure that communication to other branches in the network is not affected.

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figure 1

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figure 2

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image 3

Step 4: Due to the presence of resonance, nodes or wiring exposed to very harsh RF fields should also be distributed to different branches (see Figure 4). Use one at each end of the cable? ? The terminal (FlexRay Electrical Physical Layer Specification v2.1 Revision B) transfers the RF induced current to the ground. This results in a lower common-mode voltage on the cable without affecting the nodes connected to other branches. Therefore, the jitter in the received data stream can be controlled within a reasonable range.

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Figure 4

Step 5: To ensure that there is always a suitable (??) terminal at both ends of the cable (see Figure 5), the end node of the trunk cable should not be an optional node. The electrical position of the node along the cable must not cause the cable length to exceed 10 meters. On non-optional nodes, a short stub ("1 meter") can be introduced. Even with greater flexibility, the active star does not have to be at the cable end.

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Figure 5

Verification and optimization

Following these five steps helps build a FlexRay topology that is robust in terms of electronic properties. Simulations are recommended to further validate and optimize the defined topology. The Monte-Carlo simulation is used to estimate manufacturing tolerances for wire harnesses, yield ranges, and temperatures that depend on the transceiver and active star.

In addition, the FlexRay Consortium has introduced a sophisticated cable model that encompasses the skin effect of the harness. While supporting automotive manufacturers to introduce FlexRay, NXP is also constantly improving its expertise in FlexRay topology simulation.

About the FlexRay application? ? Further information on terminals, cables and connectors can be found in FlexRay Electrical Physical Layer Specification v2.1 Revision B. Electrical Physical Layer Application Note v2.1 Revision B gives some suggestions for topology design. Both specifications are available on the FlexRay Alliance website. For technical details of the TJA1080 FlexRay transceiver, check out the NXP website.

As long as you follow these recommendations, you can help reduce the power consumption of your system design with FPGAs.

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