Design of airborne HD video processing module
In order to enable pilots to read more and more clear video information, this paper studies the hardware design and logic software algorithm of the onboard HD video processing module. High-definition video display, including scaling and overlay of HD video, is implemented in the cockpit display system. Meet the system's requirements for high-definition video processing.
introduction
The development of modern aircraft cockpit display technology is changing with each passing day, and the data that needs to display various sensor information has reached a massive scale. The information obtained by pilots during different flight periods is also increasing. In order to enable pilots to read and process more accurate information during a specific flight time, and various sensor information is fused in the same coordinate system, research is needed. High-definition video processing technology in the airborne environment, researching the processing of high-definition video signals on a larger-sized display.
The high-definition video processing module is located in the display subsystem to accelerate the display of high-definition video signals for zooming and superimposing high-definition video. Meet the pilot's need for large size and high definition video display. The module receives the display command and the video data, accelerates the display of the fusion information to the display, and simultaneously receives and decodes two high-definition external video signals, and implements internal and external video processing operations in the FPGA chip, including scaling and superposition, and will process the The video information is output to the display according to different requirements.
1 HD video processing module system structure
The high-definition video processing module internally includes a graphics processor, which receives display commands and data, accelerates rendering of the graphics image, outputs the high-definition video signal, and integrates the external video signal in the FPGA, and the two channels are respectively output to the external display, and the video formats are respectively HD LVDS and HD DVI.
The main functional circuits of the HD video processing module include a graphics processor circuit, a video overlay and scaling logic circuit, a codec circuit, and a power supply reset clock circuit. The block diagram of the module system is shown in Figure 1.
2 HD video processing module hardware circuit design
2.1 graphics processor circuit
The graphics processor circuit is primarily responsible for internal HD video generation and video output control. It accelerates the drawing data and commands generated by the 2D and 3D graphics acceleration pipelines and stores them in the video memory. The output control unit outputs the video signals in the corresponding format according to the corresponding format.
The graphics processor uses AMD's M9000 chip, which supports high-definition video processing, supports 2D and 3D graphics hardware acceleration, OpenGL graphics interface standard, working frequency up to 250MHz, 64MByte of memory capacity, two independent display output channels, Choose LVDS, DVI, VGA, TV and parallel LCD interfaces. In this design, the graphics processor generates an internal video signal with a resolution of 1920 & TImes; 1080 and a refresh rate of 60 Hz.
2.2 Video overlay and scaling logic
The video overlay and scaling logic circuit includes two parts of the FPGA and SRAM circuits, which perform superposition operation and scaling of the inner video and the outer video. From the perspective of FPGA, its functional interface includes: one high-definition video signal, generated by the graphics processor, two high-definition external video signals, decoded by the decoder and output to the FPGA chip, one high-definition DVI video output, external output all the way High-definition DVI signal, one dual LVDS video output, meets the high-definition LVDS signal output to the liquid crystal display, and finally the SRAM buffer part, realizes the video signal buffer function.
Based on the number of FPGA functional interfaces and module power consumption, this design selects the XC6SLX150-2FGG9001 chip from the SPARTAN-6 series of XILINX. The film has a total of 147,443 logical processing units, and can use up to 576 I/O pins. The logic resources are quite rich, which can meet the logic resources requirements of high-definition video scaling and overlay functions.
The SRAM memory is used to buffer video information. It uses a flip-flop to store information. The flip-flop can maintain its original state after the information is read, so the SRAM does not need to be regenerated. Even if the integration of DRAM is higher than that of SRAM, and the power consumption is small and the price is low, the current SRAM capacity is increasing, the speed is higher than that of DRAM, and the timing control is simpler than DRAM. The most important thing is that SRAM is relatively stable as a memory chip. Therefore, this design selects CYPRESS's SRAMCY7C1470BV33-167AXI as the video signal buffer. The module uses 6 SRAMs. The chip has a storage capacity of 2 M&TImes; 36 bits, 3.3V power supply, supports 167MHz bus operation, and operates at -40°C to +85°C, meeting the needs of video buffering.
2.3 codec circuit
The codec circuit is composed of a decoding circuit and an encoding circuit. The decoding circuit mainly completes the decoding function of two high-definition digital DVI videos, and transmits the digital RGB signals that are matched to the VESA-like video timing after decoding to the FPGA. The decoding circuit uses two ADV7162 AD companies. The chip is a dual-channel high-definition digital DVI decoder, supports HDMI standard 1.4a, has a programmable equalizer, each HDMI interface supports 5V power supply and hot plug detection, operating frequency up to 225 MHz, operating temperature is -40 ° C to + 85 ° C.
The encoder circuit completes the encoding function of the two channels of video, and separately converts the digital RGB video signal outputted by the FPGA into one dual LVDS signal and one high-definition DVI signal. The dual LVDS signal directly drives the liquid crystal display. The physical link has two pairs of differential clock lines and eight pairs of differential data lines. It receives parallel digital RGB signals from the FPGA and converts them into serial LVDS signals. The encoder uses NI DS90C387 to encode and transmit dual LVDS signals. The chip supports both single-pixel and dual-pixel data transmission modes. It can convert 48-bit parallel TTL data (double 24-bit color pixels) into 8 pairs. LVDS differential data line, dual pixel rate up to 112MHz, can meet the requirements of 1080p HD video encoding and drive transmission.
The other high-definition DVI signal is also encoded and converted from the FPGA chip after receiving the parallel digital RGB signal. The logical transmission content is the same as the dual LVDS signal path. The difference is that it encodes the parallel digital RGB video into serial differential TMDS. Physical link signal, the encoder adopts ADV7513 of AD company. This chip is a high-resolution multimedia interface encoder, supports DVI v1.4 protocol, its parallel transmission clock is up to 165MHz, supports 1080p video coding, and satisfies the coding format. And HD resolution requirements.
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