The best solution for software radio processing based on CPCI architecture
The basic idea of ​​software radio is based on a common, standard, modular hardware platform, through software programming to achieve various functions of the radio station, free from the hardware-based, purpose-oriented radio design method. The software implementation of the function requires the reduction of single-function, poorly-flexible hardware circuits, especially to reduce the analog link, and to digitize the processing (A/D and D/A conversion) as close as possible to the antenna. Software Radio emphasizes the openness and comprehensive programmability of the architecture, changing the hardware configuration structure through software updates, and implementing new functions. Software radio uses a standard, high-performance open bus architecture to facilitate the continuous upgrading and expansion of hardware modules.
The software radio system consists of antennas, broadband RF converters, A/D, D/A converters and DSP (Digital Signal Processor). The key component of software radio is to replace the dedicated digital circuit with a DSP processor with strong programming ability, so that the hardware structure and function of the system are relatively independent. The DSP processor is used to perform functions such as intermediate frequency (RF), baseband and bit stream processing. The software radio hardware platform adopts modularization and is an open communication platform. Different hardware functions are implemented by loading different software (replace the card when needed). However, the software radio has a high hardware platform. It requires a broadband RF front-end, broadband A/D, D/A converter and high-speed DSP, and can operate at frequencies up to several hundred megahertz. Because the signal interference is very serious, it must operate in parallel with multiple CPUs to meet the processing speed requirements of the system. In addition, DSP processing data requires high-speed conversion, and the system bus must have a very high I/O transfer rate.
Beijing Taispeed Technology Co., Ltd. independently developed, based on CPCI architecture, in line with PICMG2.0 D3.0 standard, including dual TI TMS320C6455, Xilinx FPGA XC5VSX95T-1FF1136C development platform, is the best solution for software radio processing.
First, the system structure is as follows:
1. The AD part has 2 channels of AD input, the device adopts ADS62P49, and the maximum sampling rate supports 250MSPS, which is 14bit data. The input signal amplitude is 1V, 50 ohms, and the physical interface is SMA.
2. DA part of the two DAC outputs, the device uses AD9777, the conversion rate is 160MHz, 14bit data. The output signal amplitude is 1V, 50 ohms, and the physical interface is SMA.
Third, the DSP chip part1. DSP clock clocked at 1GHz, supporting 1.2GHz
2. Memory bus independent, onboard DDR2-500 512MB
3. The PCI interface supports Master and Slave, 32bit/33MHz or 32bit/66MHz.
4. Dual DSP and FPGA are connected by EMIF and Mcbps. EMIF supports 16bit, 32bit, 64bit width and speed of 100MHz.
5. Support 32MB-128MB Nor Flash
6. Support Gigabit network interface
7. The two C6455s are coupled together by RapidIO, with a bidirectional transfer rate of up to 10 Gbps.
Fourth, the FPGA chip partThe FPGA adopts Xilinx's new generation of high-end V5 series chips, and the model number is: XC5VSX95T-1FF1136C.
XC5VSX95T has logic module 160 x 54 maximum RAM module 1, 120Kb, DSP48E 640, CMT clock
Manage 16 RockeTIO GTPs, 20 total IObanks, and use up to 680 IOs.
1. External DDR2 memory stick, support up to 2GB.
2. External reference clock input function, the interface is SMA.
3. The external event triggers the input function and the interface is SMA.
4. Dial code input / LED light indication.
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