1, circuit design and input
Circuit design and input refers to the input of engineer circuit ideas to EDA tools through the description of certain specifications. Commonly used design methods include hardware description language (HDL) and schematic design input methods. The schematic design input method is widely used in the early stage. It selects the device, draws the schematic diagram, and completes the input process according to the design requirements. This method is somewhat intuitive, easy to understand, and rich in library resources. However, in large designs, the maintainability of this method is poor, which is not conducive to module construction and reuse. The main disadvantage is that all the schematics have to be changed after the selected chip is upgraded. At present, the most commonly used design method for large-scale engineering design is HDL design input method. The most influential HDL language is VHDL and Verilog HDL. Their common feature is to use top-down design to facilitate module division and reuse. The portability is good, the versatility is good, and the design does not change due to the different process and structure of the chip, which is more conducive to the transplantation to the ASIC. Waveform input and state machine input methods are two commonly used auxiliary design input methods: when using waveform input, Zhiyi loves to draw the excitation waveform and output waveform, and the EDA software can automatically design according to the response relationship; using the state machine input method When the designer only needs to draw the state transition diagram, the EDA software can generate the corresponding HDL code or schematic diagram, which is very convenient to use. However, it should be pointed out that the waveform input and state machine input methods can only alleviate the designer's workload in some special cases, and are not suitable for all designs.
2, functional simulation
After the circuit design is completed, the function simulation of the design is performed with a dedicated simulation tool to verify whether the circuit function meets the design requirements. Functional simulation is sometimes referred to as pre-simulation. Through simulation, errors in the design can be found in time, the design progress can be accelerated, and the reliability of the design can be improved.
3, comprehensive optimization
Synthesize (Synthesize) refers to the translation of HDL language, schematic and other design inputs into logical connections (net tables) consisting of basic logic units such as AND, OR, NOT, RAM, and flip-flops, and according to objectives and requirements (constraints) Condition) Optimize the generated logical connection and output the netlist file in standard format such as edf and edn for FPGA/CPLD manufacturer's place and router.
4, after the simulation
After the completion of the comprehensive inspection, it is necessary to check whether the comprehensive result is consistent with the design and perform the post-integration simulation. In the simulation, the integrated generated standard delay file is back-flagged into the comprehensive simulation model to estimate the impact of the gate delay. Although the integrated simulation is more accurate than the functional simulation, it can only estimate the gate delay, and can not estimate the line delay. There is still a certain gap between the simulation result and the actual situation after wiring, which is not very accurate. The main purpose of this simulation is to check if the synthesis result of the synthesizer is consistent with the design input. At present, mainstream synthesis tools are becoming more and more mature. For general design, if the designer is convinced that he is clearly marked and there is no comprehensive ambiguity, this step can be omitted. However, if the circuit structure is found to be inconsistent with the design intent after the post-layout simulation, it is often necessary to go back to the post-synthesis simulation to confirm whether the problem is due to comprehensive ambiguity.
5, implementation and layout
The essence of the comprehensive result is a logical network table composed of basic logic units such as AND, OR, NOT, Flip, RAM, etc., which has a big gap with the actual configuration of the chip. At this point, you should use the software tools provided by the FPGA/CPLD vendor to adapt the integrated output netlist to the specific FPGA/CPLD device according to the model of the selected chip. This process is called implementation. Because only the developer of the device knows the internal structure of the device, the implementation steps must use the tools provided by the device developer. The most important process in the implementation process is place and route (PAR). The so-called "Place" refers to the hardware primitive or the underlying unit in the logical netlist is properly adapted to the inherent hardware structure inside the FPGA. The pros and cons of the layout are the final result of the design (in terms of speed and area). )great influence. The so-called "route" refers to the process of properly and correctly connecting the components according to the topology structure of the layout and utilizing various connection resources inside the FPGA. The structure of the FPGA is relatively complicated. In order to obtain better implementation results, especially to ensure that the timing conditions of the design can be met, the timing-driven engine is generally used for layout and routing, so different input inputs, especially different timing constraints, are obtained. The layout and routing results generally have large differences. The structure of CPLD is relatively simple, its resources are limited and the routing resources are generally cross-connected matrix. Therefore, the layout and routing process of CPLD is relatively simple and clear, and is generally called the adaptation process. In general, the user can specify the optimization criteria of the place and route by setting parameters. In general, the optimization target has two main aspects, area and speed. Generally, according to the main contradiction of the design, the selection area or speed or the balance of the two is optimized. However, when the two conflict, it is more important to meet the timing constraint requirements. In this case, the speed or timing optimization target is better.
6, timing simulation and verification
The delay information of the layout and layout is back-labeled into the design netlist. The simulation performed is called timing simulation or post-layout simulation, also called post-simulation. The simulation delay file contains the most complete delay information, including not only the gate delay, but also the actual routing delay, so the simulation after placement and routing is the most accurate, which can better reflect the actual working condition of the chip. In general, the post-wiring simulation step must be performed. After the placement and routing, the simulation can check whether the design timing is consistent with the actual operation of the FPGA to ensure the reliability and stability of the design.
The main purpose of functional simulation is to verify that the circuit structure and function of the language design are consistent with the design intent.
——The main purpose of the post-synthesis simulation is to verify whether the integrated circuit structure is consistent with the design intent and whether there is a ambiguous comprehensive result.
-- The main purpose of post-layout simulation is to verify that there are timing violations.
7, board level simulation and verification
In some high-speed designs, third-party board-level verification tools are required for simulation and verification. These tools can better analyze the signal characteristics such as signal integrity and electromagnetic interference of high-speed design by simulating the design of IBIS and HSPICE models.
8, debugging and loading configuration
The final step in design development is to debug online or write the generated configuration file to the chip for testing. Oscilloscopes and logic analyzers are the primary debugging tools for logic design. The traditional logic function board level verification method uses logic analyzer to analyze signals. FPGA and PCB designers are required to reserve a certain number of FPGA pins as test pins. When writing FPGA code, the signals to be observed are used as output signals of the module. In the integrated implementation, these output signals are locked to the test pins, and then the probes of the logic analyzer are connected to the test pins to set the trigger conditions for observation.
If there is a problem with any simulation or verification steps, you will need to return to the appropriate steps to change or redesign the main debugging tools for the logic design based on the error location. The traditional logic function board level verification method uses logic analyzer to analyze signals. FPGA and PCB designers are required to reserve a certain number of FPGA pins as test pins. When writing FPGA code, the signals to be observed are used as output signals of the module. In the integrated implementation, these output signals are locked to the test pins, and then the probes of the logic analyzer are connected to the test pins to set the trigger conditions for observation.
If there is a problem with any simulation or verification steps, you will need to return to the appropriate step to change or redesign based on the error location.
Rich routing resources in FPGA
The routing resources connect all the cells inside the FPGA, and the length and process of the wires determine the driving capability and transmission speed of the signals on the wires. The FPGA chip has a wealth of wiring resources inside, and is divided into four different categories according to the process, length, width and distribution position.
The first type is the global routing resource for the internal clock of the chip and the global reset/set wiring;
The second type is a long-term resource for completing the wiring of the high-speed signal between the chip banks and the second global clock signal;
The third category is short-term resources used to complete the logical interconnection and routing between basic logic cells;
The fourth category is distributed routing resources for control signal lines such as proprietary clocks and resets.
In practice, the designer does not need to directly select the routing resources, and the layout router can automatically select the routing resources to connect the various module units according to the topology and constraints of the input logical network table. In essence, there is a close and direct relationship between the use of routing resources and the results of the design.
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