Building Distributed RAM Using LUT in 3 Series FPGAs (2)

October 12, 2024

Distributed RAM supports the following single-port RAM and dual-port RAM types:

SRAM with asynchronous write/synchronous read, where synchronous reads can be implemented using flip-flops associated with distributed RAM.

A DRAM with one synchronous write port and two asynchronous read ports, wherein the principle of synchronous synchronous read is the same as the former.

Figure 1 shows an illustration of SRAM and DRAM. It can be seen that the DRAM has a read/write port and a separate read port. Any write operation to the D input port and read operation to the SPO output port can be performed simultaneously and independently of the read operation of the other read port, the DPO.

Building Distributed RAM Using LUT in 3 Series FPGAs (2)

Figure 1 Schematic of SRAM and DRAM
The write operation is a single clock edge operation under the control of the write enable signal WE. WE default is highly efficient. When write enable is high, the write address is latched on the clock edge and data is written to the D port of the selected RAM area. The read operation is purely combined: the address port of the single-port or dual-port mode is asynchronously accessed, and the delay time is consistent with the logical delay of the LUT.

If the read and write operations occur at the same time, the data reflected in the memory unit is output when the data is written synchronously. This mechanism is similar to the mechanism of the block RAM in the Spartan-3 series FPGA. The User Guide is called "WRITE_MODE=WRITE_FIRST". Figure 2 shows the timing diagram for this operation.

Building Distributed RAM Using LUT in 3 Series FPGAs (2)

Figure 2 Timing diagram of simultaneous reading and writing operations
Summarizing the several operations mentioned above, you can get the following characteristics:
Only one clock edge is required for a write operation.
Read operations only require a logical read time.
The output is asynchronous and its delay is only related to the logical delay of the LUT.
Data and address inputs are stored on the write clock and have specific settling time requirements, but do not require hold time.
The A[#:0] ports of the dual port RAM are read and write addresses, and the DPRA[#:0] ports are independent read-only addresses.

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