The principle and use of the SL16 shift register of Xilinx FPGA
A shift register with a shift length can be defined.
Just use a lut to implement a 16-bit shift register.
SRL16 is a 16bit shift register lookup table // 16-Bit Shift Register Look-Up-Table (LUT)
16 FF shift functions can be implemented in one LUT!
SSRL16 SRL16_inst (
.Q(Q), // SRL data output
.A0(A0), // Select[0] input
.A1(A1), // Select[1] input
.A2(A2), // Select[2] input
.A3(A3), // Select[3] input
.CLK(CLK), // Clock input
.D(D) // SRL data input
);
Xilinx official website description - principle
The input A3, A2, A1, and A0 select the output length of the shift register. The shift register may be a fixed, staTIc length or it may be dynamically adjusted.
The shift register LUT contents are iniTIalized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value Of four zeros (0000) so that the shift register LUT is cleared during configuraTIon.
The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transiTIon. During subsequent Low-to-High clock transitions data is shifted to the next highest bit position as new data is Loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.
Here are a few points,
- The initial value of the shift register can be initialized with the INIT attribute;
- the length of the shift register is determined by the value of the address line;
- Shift data is input from D terminal, Q terminal output
- The data moved in first is MSB
Xilinx official website description - Static Length Mode
To get a fixed length shift register, drive the A3 through A0 inputs with static values. The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula:
Length = (8*A3) +(4*A2) + (2*A1) + A0 +1
If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones (1111), it is 16 bits long.
Xilinx official website description - Dynamic Length Mode
The length of the shift register can be changed dynamically by changing the values ​​driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero ( 0), the length of the shift register changes from 16 bits to 8 bits.
Internally, the length of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output.
Inputs Output
Am CLK DQ
Am XXQ(Am)
Am ↑ DQ(Am-1)
m= 0, 1, 2, 3
Here are a few tips:
- The shift register is variable length
- The length change is specified by the address line
- The internal register length is constant, but the length of the interception has changed.
- The data is first shifted into A0, then to A1, and so on. Finally, it is output from Am-1 of the specified length. For example, A=8, the data is input from address 0 and output from address 7, so that the effective shift length is Is 8.
Description of Xilinx official website - VHDL instantiation example
-- SRL16: 16-bit shift register LUT operating on posedge of clock
-- All FPGAs
-- Xilinx HDL Libraries Guide version 7.1i
SRL16_inst : SRL16
-- The following generic declaration is only necessary if you wish to
-- change the initial contents of the SRL to anything other than all
-- zero's.
Generic map (
INIT => X"0000")
Port map (
Q => Q, -- SRL data output
A0 => A0, -- Select[0] input
A1 => A1, -- Select[1] input
A2 => A2, -- Select[2] input
A3 => A3, -- Select[3] input
CLK => CLK, -- Clock input
D => D -- SRL data input
);
-- End of SRL16_inst instantiation
Copy code
Description of Xilinx official website - Verilog instantiation example
-- SRL16: 16-bit shift register LUT operating on posedge of clock
- All FPGAs
-- Xilinx HDL Libraries Guide version 7.1i
SSRL16 SRL16_inst (
.Q(Q), // SRL data output
.A0(A0), // Select[0] input
.A1(A1), // Select[1] input
.A2(A2), // Select[2] input
.A3(A3), // Select[3] input
.CLK(CLK), // Clock input
.D(D) // SRL data input
);
// The following defparam declaration is only necessary if you wish to
// change the initial contents of the SRL to anything other than all
// zero's. If the instance name to the SRL is changed, that change
// needs to be reflected in the defparam statements.
Defparam SRL16_inst.INIT = 16'h0000;
// End of SRL16_inst instantiation
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