In FPGA design, we are often used to add a reset signal to the port declaration of the HDL file, but ignore the resource consumption it brings. After careful analysis, there are so many effects:
Resetting the network requires wiring resources that cause the routing signals of the remaining signals to be affected, reducing their freedom of routing.
Increased cabling networks often require higher speed chips.
Resetting the network occupies a lot of wiring resources, making the time of Place&Route greatly increased. If the computer is a classic machine, it is very painful.
The reset signal requires a large amount of logic resources. The reset signal requires the use of a dedicated reset pin of the flip-flop.
An operational reset signal often results in an additional gate operation or a dedicated reset signal input before the input of the D flip-flop.
Increase the size of the entire design.
Additional logic consumption reduces system performance.
Blocking the use of high-efficiency features such as the Xilinx FPGA-specific SRL16E shift register.
The SRL16E can implement up to 16 triggers in a single LUT.
The virtual trigger implemented by SRL16E does not support the reset operation, which makes the synthesis tool unable to effectively utilize the SRL16E resource when the reset operation is performed in the HDL design. It is possible to increase resource consumption by up to 16 times.
In the white paper WP275.pdf on the Xilinx website: "Get your PrioriTIes Right - Make your Design Up to 50% Smaller" mentioned how the reset signal affects the utilization of FPGA resources. Interested friends can read it.
To sum up, Xilinx FPGA design generally does not need to insert a global reset network, so we do not have to add a reset port to each module when writing a program, which is convenient for program writing, reduces compile time, and reduces resources. Occupied. In most cases, all flip-flops and RAM can be preset to the initial state during reconfiguration or power-up, so global reset is completely unnecessary, because all signals have a clear initial value! Xilinx FPGAs are fully validated, so scanning logic and running test vectors are no longer necessary operations, and global resets are no longer needed as part of these operations.
The reset operation also affects the device's resource usage, layout, and implementation. Therefore, you must use a reset operation in time to carefully design the reset network locally. The design of the FPGA is really profound and profound. Many of the feelings are conventional things. In actual implementation, sometimes it is completely unreasonable. Welcome everyone to discuss.
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