MSP430-based timer Timer_A introduced

April 04, 2023

First, the timer TImer_A introduced

TImer_A is a 16-bit timer/counter with multiple capture/compare registers. There are several registers, TAxCTL, TAxR, TAxCCTLn, TAxIV, TAxEX0. The main one is the TAxCTL register, which determines the input clock signal of TImer_A, the working mode of TImer_A, the start and stop of Timer_A, and the application for interrupt. Interrupts can come from timer overflow or any of the characteristics of the capture/compare register Timer_A include:

Asynchronous timer/counter with 4 operating modes

Selectable clock source

Configurable PWM output function

Asynchronous input and synchronization latch

Second, Timer_A operation

1. 16-bit timer/counter

The 16-bit timer/counter register TAxR increments or decrements at the rising edge of each clock signal. TAxR can be cleared by setting TACLR. The Timer_A mechanism diagram is as follows:

MSP430-based timer Timer_A introduced

2. Clock source selection and frequency division

The timer clock TACLK can select from ACLK, SMCLK or external TAxCLK. The clock source is selected by the TASSELx bits. The selected clock source can directly reach the timer, or it can reach the timer after the IDx bit is divided by 2, 4 or 8. The selected clock source can be 2, 3, 4, 5, 6, 7 or 8 through IDEXx. Frequency division. When TACLR is set, the timer clock source divider is reset.

3. Start timer

The timer starts counting at the same time that the MC â€ {0} clock source is activated

When the timer is operating in up-count mode or up/down-count mode, writing 0 to TAxCCR0 can stop the timer. The timer can be restarted by writing a non-zero value to TAxCCR0. In this case, the timer counts from zero.

4. Timer mode control

MSP430-based timer Timer_A introduced